Application of a Silicon Compiler to VLSI (Very Large Scale Integrated Circuits) Design of Digital Pipelined Multipliers (1984)
Defense Technical Information Center · leaf 28
State tiling is controlled not by a two-phase son- ewer lap ping clock/ which is somewhat standard in NMOS VLSI/ hat by a three-phase clock which drives the register circuit shown in figure 2.4. This clocking scheme appar¬ ently allows a more compact layout of the register erga- nelle, but requires… … Figure 2.4 flacPitts Register Circait and Timing Diagram. 25
Carlson,D J · Naval postgraduate school monterey ca · Integrated circuits · Silicon · Compilers · Digital computers · INPUT · Output · Digital systems · Isolation · Theses · Storage
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